@regehr Some more details:
- the D/V and toolchain costs are amortized. Broadly speaking, the bigger your ecosystem/market share, the bigger your ability to absorb that cost.
- This holds for what ARM would call "application" cores; oversimplifying a bit, it's essentially a constant overhead on the design that adds some extra area and pipe stages. It's more onerous for smaller cores, but you need to be really small.

@regehr Eventually, there's nowhere left to hide. For applications where you'd use say an ARM Cortex-M0 or a bare-bones minimal RV32I CPU, I'm not aware of anything x86 past or present that would really make sense.

Intel did "Quark" a while back which I believe was either a 486 or P5 derivative, so still something like a 5-stage pipelined integer core. If you want to go even lower than that, I don't think anyone has (or wants to do) anything.

@rygorous @regehr yeah, this

@steve @regehr Anyway, take that with whatever amount of salt you want, but Intel and AMD both are strongly incentivized to seriously look at this.

They for sure would prefer to sell you x86s because they have decades of experience with that, but they're looking at what it costs them to do it both in capex and in how much it hurts the resulting designs.

And for the latter, the consistent answer has been "a bit, but not much".

@rygorous @steve I've seen part of a convincing / complete formal spec for x86 and I would run away from any effort to validate an implementation of this

@regehr @steve Anecdotally, there's at least 3 (Intel, AMD, Centaur) companies that do this on the regular, and one of them (Centaur) is quite small as such things go.

I wouldn't want to do it either, but the other thing you gotta keep in mind is that the CPU core, while important, is only part of a SoC and ISA has very little impact on the "everything else".

@rygorous @steve sure sure

@regehr @steve For example, it's a goddamn NIGHTMARE doing a high-performance memory subsystem for absolutely anything.

This whole "shared memory" fiction we're committed to maintaining is a significant drag on all HW, but HW impls of it are just in another league perf-wise than "just" building message-passing and trying to work around it in SW (lots have tried, but there's little code for it and it's a PITA), so we're kind of stuck with it.

@regehr @steve Basically almost everything that _all_ major ISAs pretend is true about memory at the ISA level is an expensive lie, but one that ~ALL the SW depends on.

@regehr @steve To wit: virtual memory is a lie, by design. Uniform memory is a lie. Shared instruction/data memory is a lie. Coherent caches are a lie, caches would rather be _anything_ else. Buses are a lie. Memory-mapped IO is IO lying about being memory. Oh and the data bits and wires are small and shitty enough now that they started lying too and everything is slowly creeping towards ECCing all the things

@regehr ARM and x86 are both godawful messes. Because that's what happens to all successful ISAs - they get cruft.

So - once you move the "old junk" to a slow path and recommend people don't use them, then you have ARM64 vs x64. And now they're pretty close in oddness, and the difference in decoder area/power is small enough that it doesn't matter.

@TomF @regehr I’m not educated or experienced with this level of detail. So speaking purely as a consumer, how is it that the apple silicon so vastly out performs similar x86-64 machines while also using less power and generating less heat?
Is it possible to make an x86-64 system that performs as well (that is, with the same ratio of power consumption and heat)?
Marketing *clearly* wants us to think that it’s ARM. All I know is my personal interactions with the two as a regular user of both PCs and Macs.

@photex @regehr Apple have an amazing team of engineers, and they focus very well. They are happy to ignore performance of legacy apps and tune for only modern use cases, and work closely with their compiler teams. The magic of a tight ecosystem!

If it was "just ARM" then the 20-30 other vendors that use ARM would also be seeing these amazing results (and would have for the last 40 years). Remember that Intel used to make ARM cores, too! Clearly, that is just marketing.

@photex @regehr I should modify this - "Apple CURRENTLY have an amazing team of engineers." We're people. We can move around. Those folks didn't hatch from eggs laid by Steve Jobs - they came from other companies, and they can go back to other companies

@TomF @regehr yes. I would absolutely *love* to see an x86-64 laptop hit this same level of price:performance:battery-lifetime. Some place like framework maybe. Everyone else seems to be repackaging Chinese designs from like one or two shops and those places don’t experience sufficient market pressure to improve the situation yet.
Fingers crossed though that it happens.

@photex @regehr The savings are all through the app/OS/device stack. Again - that is the advantage of a vertical integration and a controlled ecosystem. I doubt any significant % is due to the ISA itself. Apple also used to use x86...

@TomF @photex @regehr yeah, it's one of those classic "oh man what crazy optimization are they doing over there!?" And it turns out there's a few, but the main thing is that when you go into sleep the firmware actually, successfully, puts all the components into their deepest sleep states. A thing PC laptop vendors can only dream about. (Plus a morbillion small accumulated improvements across the entire stack)

@TomF @photex @regehr another example, I have a super nice ASUS AMD phoenix APU based laptop, which has great battery life. However, one of AMDs newer power saving features, CPPC (broad strokes, adapting clocks with lower latency to get into low power states, faster), just does not work with my specific laptop, because ASUS haven't shipped an updated AGESA with a fix for the feature. (Unclear whether this is for good reason, but I assume it's just costly to re-validate and they don't want to)